1. Field of the Invention
The present invention generally relates to power supply step-down circuits and semiconductor devices, and more particularly to a power supply step-down circuit for stepping down an input power supply voltage and to a semiconductor device having such a power supply step-down circuit.
2. Description of the Related Art
Due to improvements made in the semiconductor producing processes that form extremely small patterns, the size of semiconductor integrated circuits (LSI circuits) within the semiconductor device has become extremely small, and voltages that may be applied to the LSI circuits have become low. On the other hand, from the point of view of the user of the LSI circuit, there are demands to use the same power supply voltage as the conventional LSI circuit, because of the desire to use the same power supply unit or the like as the conventional LSI circuit. Accordingly, a power supply step-down circuit is provided within the LSI circuit, so that a relatively low voltage is supplied within the LSI circuit even when an external power supply voltage applied to the LSI circuit is relatively high.
The current consumption of the LSI circuit is determined by the current value which changes proportionally to a frequency of a clock supplied to a circuit part within the LSI circuit and in synchronism with the clock. For this reason, it is necessary to set the current consumption of the power supply step-down circuit to a relatively large value on the order of several hundred μA to several mA, for example, so that a high reaction speed of the power supply step-down circuit is obtainable. In this specification, such an operation mode of the LSI circuit will be referred to as a normal operation mode.
On the other hand, there are LSI circuits that have an operation mode for reducing the current consumption by stopping the supply of the clock when the LSI circuits do not need to operate. In this specification, such an operation mode of the LSI circuit will be referred to as a standby mode. One example of the LSI circuit having the standby mode is an LSI circuit that includes a CPU and/or logic circuit. Normally, the standby mode requires the supply of the clock to be stopped, and the current consumption of the LSI circuit to be constant and on the order of approximately 10 μA to approximately 1 μA or less. For this reason, in the standby mode, it is not possible to step down the input power supply voltage using the power supply step-down circuit having the relatively large current consumption on the order of several hundred μA to several mA, for example.
Accordingly, a step-down circuit for the normal operation mode and a step-down circuit for the standby mode are provided in the conventional LSI circuit, and the step-down circuit for the standby mode is constantly operated. In the normal operation mode, the step-down circuit for the normal operation mode is operated in addition to the step-down circuit for the standby mode. Hence, the current consumption of the power step-down circuit part as a whole is reduced in the standby mode.
But when the step-down circuit for the normal operation mode and the step-down circuit for the standby mode are provided separately within the LSI circuit, there is a limit to reducing the area occupied by the step-down circuit part as a whole. Hence, it is conceivable to provide a single power step-down circuit integrally having the step-down circuit for the normal operation mode and the step-down circuit for the standby mode. In this conceivable case, there is a circuit part that may be used in common between the step-down circuit for the normal operation mode and the step-down circuit for the standby mode, thereby enabling reduction of the area occupied by the power step-down circuit as a whole. The step-down circuit for the normal operation mode and the step-down circuit for the standby mode may be switched depending on the operation mode of the LSI circuit so that only one of the step-down circuits operates at time. Since the current consumption of the LSI circuit in the standby mode is constant and small, the step-down circuit for the standby mode may have a relatively slow reaction speed, and it is possible to reduce the current consumption of the step-down circuit for the standby mode.
FIG. 1 is a circuit diagram showing a conceivable LSI circuit that is provided with a single power supply step-down circuit integrally having a step-down circuit for normal operation mode and a step-down circuit for standby mode.
The LSI circuit includes input terminals 1 and 2, a single power supply step-down circuit 10, and an output terminal 9 that are connected as shown in FIG. 1. The power supply step-down circuit 10 integrally has a step-down circuit 7 for the normal operation mode and a step-down circuit 8 for the standby mode. The power supply step-down circuit 10 includes a constant voltage source 3, a differential amplifier (or an operational amplifier) 4, an output transistor 5, an inverter, and the step-down circuits 7 and 8. In this particular case, the output transistor 5 is formed by a P-channel transistor. An input power supply voltage is input to the input terminal 1, and a mode signal that indicates the operation mode of the LSI circuit is input to the input terminal 2.
For example, the mode signal that is input to the input terminal 2 has a low level in the normal operation mode, and a bias current within the differential amplifier 4 and the constant voltage source 3 becomes high, to thereby select the step-down circuit 7 for the normal operation mode having a low resistance. Since the bias current is high, the operation speed of the differential amplifier 4 becomes high, and the resistance of the differential amplifier 4 becomes low. Consequently, the charging and discharging speeds of the parasitic capacitance at a node N101 that connects the differential amplifier 4 and the step-down circuit 7 for the normal operation mode becomes high, and the reaction speed of the power supply step-down circuit 10 as a whole becomes relatively high, but the current consumption of the power supply step-down circuit 10 as a whole becomes relatively large.
On the other hand, when the mode signal having a high level and indicating the standby mode is input to the input terminal 2, the bias current within the differential amplifier 4 and the constant voltage source 3 becomes low, to thereby select the step-down circuit 8 for the standby mode having the high resistance. Since the bias current is low, the current consumption of the differential amplifier 4 becomes small, but the reaction speed of the differential amplifier 4 becomes low. Furthermore, because the differential amplifier 4 has a high resistance, the current consumption of this circuit part becomes small. However, the charging and discharging speeds of the parasitic capacitance at the node N101 becomes low, and the reaction speed of the power supply step-down circuit 10 as a whole becomes relatively low, but the current consumption of the power supply step-down circuit 10 as a whole becomes relatively small.
Next, a description will be given of the operation of the power supply step-down circuit 10 when the operation mode of the LSI circuit is switched from the standby mode to the normal operation mode.
FIG. 2 is a timing chart for explaining the operation of the power supply step-down circuit 10 shown in FIG. 1. In FIG. 2, (a) shows the mode signal, (b) shows the clock that is supplied to the circuit part within the LSI circuit, (c) shows an output current of the power supply step-down circuit 10, (d) shows a voltage at a node N100 connecting the differential amplifier 4 and a gate of the output transistor 5, and (e) shows an output voltage (stepped down power supply voltage) that is output from the output terminal 9. FIG. 2 shows a case where the operation mode of the LSI circuit undergoes a transition from the normal operation mode to the standby mode.
As shown in FIG. 2, the during the low-level period of the mode signal that indicates the normal operation mode and is input to the input terminal 2, the clock is supplied to the circuit part within the LSI circuit. In this normal operation mode, the LSI circuit is in a state where the current consumption thereof is large, that is, the output current of the power supply step-down circuit 10 is high.
On the other hand, when the mode signal that is input to the input terminal 2 makes a transition to the high level indicating the standby mode, the supply of the clock within the LSI circuit stops, and the output current of the power supply step-down circuit 10 rapidly decreases as indicated by an arrow in FIG. 2(c). In this state, although the voltage at the node N100 connecting to the gate of the output transistor 5 should rise immediately so that the output voltage from the output terminal 9 will not change before and after the operation mode switches, the switching to the step-down circuit 8 for the standby mode having the relatively slow reaction speed is already made in the power supply step-down circuit 10, and it takes time for the voltage at the node N100 to rise.
As a result, even though the output current flowing to the output terminal 9 decreases, the voltage at the node N100 remains low. Consequently, an excessively amount of current flows to the output terminal 9 to increase the output voltage that is output from the output terminal 9, and in a worst case scenario, the output voltage rises to the same potential as the input power supply voltage that is input to the input terminal 1. If the output voltage rises to the same potential as the input power supply voltage, the voltage at the node N100 will cause the output transistor 5 to completely turn OFF, and the output voltage will decrease depending on the current consumption of the LSI circuit. But since the current consumption of the LSI circuit in the standby mode is small, it takes time for the output voltage to drop to the original or proper potential.
For example, a Japanese Laid-Open Patent Application No.5-21738 proposes a power supply voltage step-down circuit for providing a stable internal power supply voltage regardless of a change in the power consumption within the LSI circuit.
Therefore, in the case of the conceivable LSI circuit shown in FIG. 1 in which the area occupied by the power supply step-down circuit is reduced by providing a single power supply step-down circuit that integrally has the step-down circuit for the normal operation mode and the step-down circuit for the standby mode, the output voltage may assume the same potential as the input power supply voltage for a long time when the operation mode of the LSI circuit makes a transition from the normal operation mode to the standby mode. But when the output voltage becomes the same potential as the input power supply voltage for the long time, a relatively high input power supply voltage is applied to the circuit part within the LSI circuit, which originally should not be applied with the input power supply voltage. For this reason, there were problems in such a case that the reliability of the LSI circuit will deteriorate, and the serviceable life of the LSI circuit will be shortened.